====== EZ-USB FX2G3 ======
USB 2.0 @ 480MHz (High Speed)

Package: 104 LGA (8x8mm)

Temperaure range: -45 .. 85 °C

Operating Voltage: 1.7V to 3.6 V

GPIF/FIFO 16bit

===== Variants =====
^ part # ^ MCU ^ SRAM ^ Flash ^ SCB # ^ Peripherals ^
| CYUSB2315-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 256 KB | 1 | I2C |
| CYUSB2316-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 256 KB | 3 | I2C, SPI, CAN |
| CYUSB2317-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI |
| CYUSB2318-BF104AXI(T) | M4(FP,MPU)@150 MHz/M0+(MPU)@100 MHz | 1024 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI, Crypto |

<code>
CY = Cypress
  USB = USB Controller
     2 = USB 2.0
      xxx = part number
         -BF104AX = LGA Package
                 I = Industrial
                  T = Tape and reel
</code>

===== Memory Map =====

^ start address ^ end address ^ used for ^ comment ^
| 0x00 00 00 00 | 0x01 ff ff ff | Code | Program code region. Data can also be placed here. It includes the exception vector table, which starts at address 0. |
| 0x00 00 00 00 | 0x00 01 ff ff | ROM | size = 128 kB |
| 0x08 00 00 00 | 0x08 01 ff ff | SRAM | size = 128 kB |
| 0x10 00 00 00 | 0x10 07 ff ff | Internal application flash | size = up to 512 kB |
| 0x14 00 00 00 | 0x14 00 7f ff | Auxiliary flash, can be used for EEPROM Emulation | size = 32 kB |
| 0x16 00 00 00 | 0x16 00 7f ff | SFlash | size = 32 kB |
| 0x1c 00 00 00 | 0x1c 0f ff ff | High bandwidth DMA buffer SRAM | size = up to 1 MB |
| 0x20 00 00 00 | 0x3f ff ff ff | reserved | |
| 0x40 00 00 00 | 0x5f ff ff ff | Peripheral | All peripheral registers. Code cannot be executed from this region. CM4 bit-band in this region is not supported in EZ-USBTM FX2G3. |
| 0x60 00 00 00 | 0x9f ff ff ff | external RAM | Quad SPI: Code can be executed from this region. |
| 0xA0 00 00 00 | 0xDf ff ff ff | external device | not used |
| 0xe0 00 00 00 | 0xe0 0f ff ff | Private Peripheral Bus | Provides access to peripheral registers within the CPU core |
| 0xe0 10 0a 00 | 0xff ff ff ff | device | device specific system registers |

===== Pins =====
  * ePad
  * A1..A56
  * B1..B48


^ Pin ^ Signal name ^ description ^
| ePAD | GND |  |
| A1 | P0CTL2  |  |
| A2 | P0CTL1  |  |
| A3 | VDDIOXTAL |  |
| A4 | XTALOUT |  |
| A5 | XTALIN |  |
| A6 | GND  |  |
| A7 | V33 |  |
| A8 | DPLUS |  |
| A9 | DMINUS |  |
| A10 | GND |  |
| A11 | VDDD |  |
| A12 | GND |  |
| A13 | P0CLK |  |
| A14 | Reserved |  |
| A15 | I2C-SCL0 (SCB0) |  |
| A15 | UART-RX0 (SCB0) |  |
| A16 | I2C-SDA0 (SCB0) |  |
| A16 | UART-TX0 (SCB0) |  |
| A17 | VDDIO |  |
| A18 | P0D0 |  |
| A19 | P0D1 |  |
| A20 | P0D2 |  |
| A21 | P0D3 |  |
| A22 | P0D4 |  |
| A23 | P0D5 |  |
| A24 | P0D6 |  |
| A25 | P0D7 |  |
| A26 | GND |  |
| A27 | VDDIOP0_CTRL  |  |
| A28 | GND |  |
| A29 | P0CTL5 |  |
| A30 | P0CTL6 |  |
| A31 | P0CTL9  |  |
| A32 | VDDIOP0 |  |
| A33 | GPIO2 |  |
| A33 | UART-TX0 |  |
| A33 | I2C-SDA0 (SCB5) |  |
| A33 | SPI-CS0 (SCB5) |  |
| A33 | CAN1-RX |  |
| A34 | PMODE |  |
| A34 | SPI-MOSI (SCB5) |  |
| A34 | CAN1-TX |  |
| A35 | P0CTL0  |  |
| A36 | GPIO1 |  |
| A36 | UART-RX0 |  |
| A36 | I2C-SCL0 (SCB5) |  |
| A36 | SPICLK (SCB5) |  |
| A37 | P0CTL3 |  |
| A38 | P0CTL4 |  |
| A39 | P0CTL7 |  |
| A40 | P0CTL8 |  |
| A41 | GND |  |
| A42 | XRES |  |
| A43 | VDDIOP0_CTRL |  |
| A44 | VBUSDETECTN |  |
| A45 | P0D8 |  |
| A46 | P0D9 |  |
| A47 | P0D10 |  |
| A48 | P0D11 |  |
| A49 | P0D12 |  |
| A50 | P0D13 |  |
| A51 | P0D14 |  |
| A52 | P0D15 |  |
| A53 | GND |  |
| A54 | CLKOUT |  |
| A55 | VDDIOP0 |  |
| A56 | GND |  |
| B1 | DNU |  |
| B2 | DNU |  |
| B3 | DNU |  |
| B4 | DNU |  |
| B5 | DNU |  |
| B6 | DNU |  |
| B7 | DNU |  |
| B8 | GND |  |
| B9 | DNU |  |
| B10 | DNU |  |
| B11 | DNU |  |
| B12 | DNU |  |
| B13 | DNU |  |
| B14 | RESREF |  |
| B15 | TDO / SWO |  |
| B15 | PDM3-CLK0 |  |
| B15 | UART-TX1 (SCB4) |  |
| B15 | I2C-SCL1 (SCB4) |  |
| B15 | SPICLK (SCB4) |  |
| B16 | TDI |  |
| B16 | PDM3-DATA0 |  |
| B16 | UART-RX1 (SCB4) |  |
| B16 | I2C-SDA1 (SCB4) |  |
| B16 | SPICS0 (SCB4) |  |
| B17 | TMS / SWDIO |  |
| B17 | PDM3-CLK1 |  |
| B17 | UART-RTS1 (SCB4) |  |
| B17 | SPI-MOSI (SCB4) |  |
| B18 | TCLKSWDCLK |  |
| B18 | PDM3-DATA1 |  |
| B18 | UART-CTS1 (SCB4) |  |
| B18 | SPI-MISO (SCB4) |  |
| B19 | GPIO |  |
| B19 | SWDRST |  |
| B20 | PDMDATA |  |
| B20 | TCPWM4_N |  |
| B21 | GPIO4 |  |
| B21 | SPI-MISO (SCB5) |  |
| B22 | SPICLK (SMIF)  |  |
| B22 | UART-RX1 (SCB6) |  |
| B22 | I2C-SCL1 (SCB6) |  |
| B23 | SPICS0 (SMIF) |  |
| B23 | UART-TX1 (SCB6) |  |
| B23 | I2C-SDA1 (SCB6) |  |
| B24 | SPICS1 (SMIF) |  |
| B25 | CAN0-TX |  |
| B25 | PDM0-DATA1 |  |
| B25 | UART-TX0 (SCB4) |  |
| B25 | I2C-SDA0 (SCB4) |  |
| B25 | TCPWM2_N |  |
| B25 | SPICS0 (SCB4) |  |
| B26 | CAN0-RX |  |
| B26 | PDM0-CLK1 |  |
| B26 | UART-RX0 (SCB4) |  |
| B26 | I2C-SCL0 (SCB4) |  |
| B26 | TCPWM2_P |  |
| B26 | SPICLK (SCB4) |  |
| B27 | SPIDAT0 (SMIF) |  |
| B27 | UART-RX1 (SCB0) |  |
| B27 | I2C-SCL (SCB0) |  |
| B27 | SPICLK (SCB2) |  |
| B28 | SPIDAT1 (SMIF) |  |
| B28 | UART-TX1 (SCB0) |  |
| B28 | I2C-SDA (SCB0) |  |
| B28 | SPICS0 (SCB2) |  |
| B29 | SPIDAT2 (SMIF) |  |
| B29 | UART-CTS0 (SCB0) |  |
| B29 | SPI-MOSI (SCB2) |  |
| B30 | SPIDAT3 (SMIF) |  |
| B30 | UART-RTS0 (SCB0) |  |
| B30 | SPI-MISO (SCB2) |  |
| B31 | VDDIOQSPI |  |
| B32 | SPIDAT4 (SMIF) |  |
| B32 | UART-CTS0 (SCB2) |  |
| B33 | SPIDAT5 (SMIF) |  |
| B34 | SPIDAT6 (SMIF) |  |
| B34 | UART-RX1 (SCB1) |  |
| B34 | I2C-SDA1 (SCB1) |  |
| B35 | SPIDAT7 (SMIF) |  |
| B35 | UART-TX1 (SCB1) |  |
| B35 | I2C-SCL1 (SCB1) |  |
| B36 | DNU |  |
| B37 | DNU |  |
| B38 | GPIO5 |  |
| B39 | GPIO6 |  |
| B40 | VCCD |  |
| B41 | DNU |  |
| B42 | GPIO8 |  |
| B43 | GPIO9 |  |
| B44 | PDMCLK |  |
| B44 | TCPWM4_P |  |
| B45 | GPIO10 |  |
| B46 | USB2DN2 |  |
| B47 | USB2DP2 |  |
| B48 | DNU |  |



===== abbreviation dictionary =====

^ abbreviation ^ long version ^ comment ^
| A/D | | analog-to-digital |
| ABS | | absolute |
| ABUS | | analog output bus |
| AC | | alternating current |
| ADC | | analog-to-digital converter |
| AES | | Advanced Encryption Standard |
| AHB | | AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM® data transfer bus |
| Arm® | | Advanced RISC Machine, a CPU architecture |
| API | | application programming interface |
| APOR | | analog power-on reset |
| BC | | broadcast clock |
| BD | | buffer descriptors |
| BOD | | brownout detection |
| BOM | | bill-of-materials |
| BR | | bit rate | 
| BRA | | bus request acknowledge |
| BRQ | | bus request |
| CAN | | controller area network |
| CAN FD | | controller area network with flexible data rate |
| CBS | | credit-based shaping |
| CFI | | canonical format indicator |
| CI | | carry in |
| CMOS | | complementary metal-oxide-semiconductor |
| CMP | | compare |
| CO | | carry out |
| CPHA(SPI) | | clock phase |
| CPOL(SPI) | | clock polarity |
| CPU | | central processing unit |
| CPUSS | | CPU subsystem |
| CRC | | cyclic redundancy check, an error-checking protocol |
| CSD | | CAPSENSETM sigma delta |
| CSV | | clock supervisor |
| CT | | continuous time |
| CTBm | | continuous time block-mini |
| DAC | | digital-to-analog converter |
| DC | | direct current |
| DDR | | double data rate (also see SDR) |
| DES | | data encryption standard |
| DI | | digital or data input |
| DMA | | direct memory access |
| DNL | | differential nonlinearity |
| DNU | Do not use | Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections. |
| DO | | digital or data output |
| DSI | | digital signal interface |
| DSM | | Deep Sleep mode |
| DW | | data wire, same as P-DMA |
| ECC | | error correcting code |
| ECO | | external crystal oscillator |
| EEE | | Energy Efficient Ethernet (IEEE Std 802.3az) |
| EEPROM | | electrically erasable programmable read only memory |
| EMIF | | external memory interface |
| EOF | | end of frame |
| ETM | | embedded trace macrocell |
| FB | | feedback |
| FCS | | frame check sequence |
| FIFO | | first in first out |
| FLL | | frequency locked loop |
| FPU | | floating point unit |
| FSR | | full scale range |
| GHS | | Green Hills tool chain with IDE |
| GPIO | | general purpose I/O |
| HCI | | host-controller interface |
| HFCLK | | high-frequency clock |
| HSIOM | | high-speed I/O matrix |
| HSM | | hardware security module |
| I2C | | inter-integrated circuit |
| IDE | | integrated development environment |
| IF | | interface |
| ILO | | internal low-speed oscillator |
| IMO | | internal main oscillator |
| INL | | integral nonlinearity |
| I/O | | input/output |
| IOR | | I/O read |
| IOW | | I/O write |
| IP | | Internet protocol |
| IPC | | inter-processor communication |
| IPG | | inter-packet gap |
| IRA | | interrupt request acknowledge |
| IrDA | | infrared interface |
| IRES | | initial power on reset |
| IRQ | | interrupt request |
| ISR | | interrupt service routine |
| IVR | | interrupt vector read |
| JTAG | | Joint Test Action Group |
| L2CAP | | logical link control and adaptation protocol |
| LAN | | local area network (IEEE Std 802) |
| LLDP | | link layer discovery protocol (IEEE Std 802.1AB) |
| LPCOMP | | low-power comparator |
| LPI | | low-power idle (IEEE Std 802.3az) |
| LRb | | last received bit |
| LRB | | last received byte |
| LSb | | least significant bit |
| LSB | | least significant byte |
| LUT | | lookup table |
| LVD | | low-voltage detection |
| MAC | | media access control (IEEE Std 802) |
| MCU | | microcontroller unit |
| MCWDT | | multi-counter watchdog timer |
| M-DMA | | memory-direct memory access |
| MDC | | management data clock |
| MII | | media independent interface |
| MISO | | master-in-slave-out |
| MMIO | | memory mapped input/output |
| MOSI | | master-out-slave-in |
| MPU | | memory protection unit |
| MSb | | most significant bit |
| MSB | | most significant byte |
| NC | Not connected | The connection may safely be used for routing space for a signal on a PCB. However, any signal connected to an NC pin must not have voltage levels higher than VIO. |
| NSP | | non-standard preamble |
| NVIC | | nested vectored interrupt controller |
| OTA | | over-the-air programming |
| OTP | | one-time programmable |
| OVD | | overvoltage detection |
| P-DMA | | peripheral-direct memory access same as DW |
| PC | | program counter |
| PCH | | program counter high |
| PCL | | program counter low |
| PCS | | physical coding sublayer |
| PD | | power down |
| PFC | | priority-based flow control (IEEE Std 802.1Qbb) |
| PGA | | programmable gain amplifier |
| PHY | | physical sublayer |
| PLL | | phase-locked loop |
| PM | | power management |
| PMA | | PSOCTM memory arbiter |
| POR | | power-on reset |
| PPB | | private peripheral bus |
| PPOR | | precision power-on reset |
| PPPoE | | point-to-point protocol over ethernet |
| PPU | | peripheral protection unit |
| PRNG | | Pseudo-Random Number Generator |
| PRS | | pseudo random sequence |
| PSRR | | power supply rejection ratio |
| PSSDC | | power system sleep duty cycle |
| PTP | | precision time protocol (IEEE Std 1588) |
| PWM | | pulse width modulator |
| RAM | | random-access memory |
| RETI | | return from interrupt |
| RFU | Reserved for Future use | Do not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in devices with a compatible footprint. |
| RF | | radio frequency |
| RISC | | reduced-instruction-set computing |
| ROM | | read only memory |
| RTC | | real-time clock |
| RW | | read/write |
| RX | | reception |
| SAR | | successive approximation register |
| SC | | switched capacitor |
| SCB | | serial communication block |
| SCB | Serial Control Block | A peripheral that can be used as I2C, UART or SPI |
| SCL | | I2C serial clock |
| SDA | | I2C serial data |
| SDR | | single data rate (also see DDR) |
| SE0 | | single-ended zero |
| SECDED | | single error correction double error detection |
| SerDes | | serializer/deserializer |
| SHA | | secure hash algorithm |
| SHE | | secure hardware extension |
| SFD | | start of frame delimiter |
| SGMII | | serial Gigabit media independent interface |
| SIE | | serial interface engine |
| SIO | | special I/O |
| SMIF | | serial memory interface |
| SMPU | | shared memory protection unit |
| SNAP | | subnetwork access protocol |
| SNR | | signal-to-noise ratio |
| SOF | | start of frame |
| SOI | | start of instruction |
| SP | | stack pointer |
| SPD | | sequential phase detector |
| SPI | | serial peripheral interface, a communications protocol |
| SPI | | serial peripheral interconnect |
| SPIM | | serial peripheral interconnect master |
| SPIS | | serial peripheral interconnect slave |
| SRAM | | static random-access memory |
| SRSS | | system resources sub-system |
| SROM | | supervisory read only memory |
| SSADC | | single slope ADC |
| SSC | | supervisory system call |
| SYSCLK | | system clock |
| SWD | | single wire debug |
| Tbit | | bit period |
| TC | | terminal count |
| TCP | | transfer control protocol |
| TCPWM | | timer/counter pulse-width modulator |
| TD | | transaction descriptors |
| TTL | | transistor-transistor logic |
| TRNG | | True Random Number Generator |
| TS | | timestamp |
| TSU | | timestamp unit|
| TX | | transmission |
| UART | | Universal Asynchronous Transmitter Receiver, a communications protocol |
| UDB | | universal digital block |
| UDP | | user datagram protocol |
| USB | | Universal Serial Bus |
| USBIO | | USB I/O |
| VLAN | | Virtual LAN (IEEE Std 802.1Q) |
| WCO | | watch crystal oscillator |
| WDT | | watchdog timer / watchdog timer reset |
| WDR | | watchdog reset |
| XIP | | execute-in-place |
| XRES | | external reset |
| XRES_N | | external reset, active LOW |
| XRES_L | | external reset I/O pin (active LOW) |
| XTAL | | crystal |