Table of Contents

STM32F429

ARM Cortex-M4 (180MHz) FPU

Memory Map

start address end address used for comment
0x0 0x1fffff Aliased to flash, system memory or SRAM depending on the BOOT pins
0x20 0000 0x7ff ffff reserved
0x800 0000 0x81f ffff flash memory
0x820 0000 0xfff ffff reserved
0x1000 0000 0x1000 ffff CCM data RAM 64 KB SRAM
0x1001 0000 0x1ffe bfff reserved
0x1ffe c000 0x1fff c00f option bytes
0x1fff c010 0x1ffe ffff reserved
0x1fff 0000 0x1fff 7a0f system memory
0x1fff 7a10 0x1fff 7fff reserved
0x1fff c000 0x1fff c00f option bytes
0x1fff c010 0x1fff ffff reserved
0x2000 0000 0x2001 bfff SRAM 112KB
0x2001 C000 0x2001 ffff SRAM 16 KB
0x2002 0000 0x2002 ffff SRAM 64 KB
0x2003 0000 0x3fff ffff reserved
0x4000 0000 0x4000 7fff APB1
0x4000 0000 0x4000 03ff TIM2
0x4000 0400 0x4000 07ff TIM3
0x4000 0800 0x4000 0bff TIM4
0x4000 0c00 0x4000 0fff TIM5
0x4000 1000 0x4000 13ff TIM6
0x4000 1400 0x4000 17ff TIM7
0x4000 1800 0x4000 1bff TIM12
0x4000 1c00 0x4000 1fff TIM13
0x4000 2000 0x4000 23ff TIM14
0x4000 2400 0x4000 27ff reserved
0x4000 2800 0x4000 2bff RTC & BKP Registers
0x4000 2c00 0x4000 2fff WWDG
0x4000 3000 0c4000 33ff IWDG
0x4000 3400 0x4000 37ff I2S2ext
0x4000 3800 0x4000 3bff SPI2 / I2S2
0x4000 3c00 0x4000 3fff SPI3 / I2S3
0x4000 4000 0x4000 43ff I2S3ext
0x4000 4400 0x4000 47ff USART2
0x4000 4800 0x4000 4bff USART3
0x4000 4c00 0x4000 4fff UART4
0x4000 5000 0x4000 53ff UART5
0x4000 5400 0x4000 5700 I2C1
0x4000 5800 0x4000 5bff I2C2
0x4000 5c00 0x4000 5fff I2C3
0x4000 6000 0x4000 63ff reserved
0x4000 6400 0x4000 67ff CAN1
0x4000 6800 0x4000 6bff CAN2
0x4000 6c00 0x4000 6fff reserved
0x4000 7000 0x4000 73ff PWR
0x4000 7400 0x4000 77ff DAC
0x4000 7800 0x4000 7bff UART7
0x4000 7c00 0x4000 7fff UART8
0x4000 8000 0x4000 ffff reserved
0x4001 0000 0x4001 6bff APB2
0x4001 0000 0x4001 03ff TIM1
0x4001 0400 0x4001 07ff TIM8
0x4001 0800 0x4001 0fff reserved
0x4001 1000 0x4001 13ff USART1
0x4001 1400 0x4001 17ff USART6
0x4001 1800 0x4001 1fff reserved
0x4001 2000 0x4001 23ff ADC1 - ADC2 - ADC3
0x4001 2400 0x4001 2bff reserved
0x4001 2c00 0x4001 2fff SDIO
0x4001 3000 0x4001 33ff SPI1
0x4001 3400 0x4001 37ff SPI4
0x4001 3800 0x4001 3bff SYSCFG
0x4001 3c00 0x4001 3fff EXTI
0x4001 4000 0x4001 43ff TIM9
0x4001 4400 0x4001 47ff TIM10
0x4001 4800 0x4001 4bff TIM11
0x4001 4c00 0x4001 4fff reserved
0x4001 5000 0x4001 53ff SPI5
0x4001 5400 0x4001 57ff SPI6
0x4001 5800 0x4001 5bff SAI1
0x4001 5c00 0x4001 67ff reserved
0x4001 6800 0x4001 6bff LCD-TFT
0x4001 6c00 0x4001 ffff reserved
0x4002 0000 0x4007 ffff AHB1
0x4002 0000 0x4002 03ff GPIOA
0x4002 0400 0x4002 07ff GPIOB
0x4002 0800 0x4002 0bff GPIOC
0x4002 0c00 0x4002 0fff GPIOD
0x4002 1000 0x4002 13ff GPIOE
0x4002 1400 0x4002 17ff GPIOF
0x4002 1800 0x4002 1bff GPIOG
0x4002 1c00 0x4002 1fff GPIOH
0x4002 2000 0x4002 23ff GPIOI
0x4002 2400 0x4002 27ff GPIOJ
0x4002 2800 0x4002 2bff GPIOK
0x4002 2c00 0x4002 2fff reserved
0x4002 3000 0x4002 33ff CRC
0x4002 3400 0x4002 37ff reserved
0x4002 3800 0x4002 3bff RCC
0x4002 3c00 0x4002 3fff Flash interface register
0x4002 4000 0x4002 4fff BKPSRAM
0x4002 5000 0x4002 5fff reserved
0x4002 6000 0x4002 63ff DMA1
0x4002 6400 0x4002 67ff DMA2
0x4002 6800 0x4002 7fff reserved
0x4002 8000 0x4002 83ff Ethernet MAC
0x4002 8400 0x4002 87ff Ethernet MAC
0x4002 8800 0x4002 8bff Ethernet MAC
0x4002 8c00 0x4002 8fff Ethernet MAC
0x4002 9000 0x4002 93ff Ethernet MAC
0x4002 9400 0x4002 afff reserved
0x4002 b000 0x4002 bbff DMA2D
0x4002 bc00 0x4003 ffff reserved
0x4004 0000 0x4007 ffff USB OTG HS
0x4008 0000 0x4fff ffff reserved
0x5000 0000 0x5006 0bff AHB2
0x5000 0000 0x5003 ffff USB OTG FS
0x5004 0400 0x5004 ffff reserved
0x5005 0000 0x5005 03ff DCMI
0x5005 0400 0x5006 07ff reserved
0x5006 0800 0x5006 0bff RNG
0x5006 0c00 0x5fff ffff reserved
0x6000 0000 0xdfff ffff AHB3
0x6000 0000 0x6fff ffff FMC bank 1
0x7000 0000 0x7fff ffff FMC bank 2
0x8000 0000 0x8fff ffff FMC bank 3
0x9000 0000 0x9fff ffff FMC bank 4
0xa000 0000 0xa000 0fff FMC control register
0xa000 1000 0xbfff ffff reserved
0xc000 0000 0xcfff ffff FMC bank 5
0xd000 0000 0xdfff ffff FMC bank 6
0xe000 0000 0xe00f ffff Cortex-M4 internal peripherals
0xe010 0000 0xffff ffff reserved

Peripherals

IRQ

IRQ Number Signal Description
0 WWDG Window WatchDog
1 PVD PVD through EXTI Line detection
2 TAMP_STAMP Tamper and TimeStamps through the EXTI line
3 RTC_WKUP RTC Wakeup through the EXTI line
4 FLASH FLASH Handler
5 RCC_IRQHandler RCC
6 EXTI0 EXTI Line0
7 EXTI1 EXTI Line1
8 EXTI2 EXTI Line2
9 EXTI3 EXTI Line3
10 EXTI4 EXTI Line4
11 DMA1_Stream0 DMA1 Stream 0
12 DMA1_Stream1 DMA1 Stream 1
13 DMA1_Stream2 DMA1 Stream 2
14 DMA1_Stream3 DMA1 Stream 3
15 DMA1_Stream4 DMA1 Stream 4
16 DMA1_Stream5 DMA1 Stream 5
17 DMA1_Stream6 DMA1 Stream 6
18 ADC ADC1, ADC2 and ADC3s
19 CAN1_TX CAN1 TX
20 CAN1_RX0 CAN1 RX0
21 CAN1_RX1 CAN1 RX1
22 CAN1_SCE CAN1 SCE
23 EXTI9_5 External Line[9:5]s
24 TIM1_BRK_TIM9 TIM1 Break and TIM9
25 TIM1_UP_TIM10 TIM1 Update and TIM10
26 TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation and TIM11
27 TIM1_CC TIM1 Capture Compare
28 TIM2 TIM2
29 TIM3 TIM3
30 TIM4 TIM4
31 I2C1_EV I2C1 Event
32 I2C1_ER I2C1 Error
33 I2C2_EV I2C2 Event
34 I2C2_ER I2C2 Error
35 SPI1 SPI1
36 SPI2 SPI2
37 USART1 USART1
38 USART2 USART2
39 USART3 USART3
40 EXTI15_10 External Line[15:10]s
41 RTC_Alarm RTC Alarm (A and B) through EXTI Line
42 OTG_FS_WKUP USB OTG FS Wakeup through EXTI line
43 TIM8_BRK_TIM12 TIM8 Break and TIM12
44 TIM8_UP_TIM13 TIM8 Update and TIM13
45 TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation and TIM14
46 TIM8_CC TIM8 Capture Compare
47 DMA1_Stream7 DMA1 Stream7
48 FMC FMC
49 SDIO SDIO
50 TIM5 TIM5
51 SPI3 SPI3
52 UART4 UART4
53 UART5 UART5
54 TIM6_DAC TIM6 and DAC1&2 underrun errors
55 TIM7 TIM7
56 DMA2_Stream0 DMA2 Stream 0
57 DMA2_Stream1 DMA2 Stream 1
58 DMA2_Stream2 DMA2 Stream 2
59 DMA2_Stream3 DMA2 Stream 3
60 DMA2_Stream4 DMA2 Stream 4
61 ETH Ethernet
62 ETH_WKUP Ethernet Wakeup through EXTI line
63 CAN2_TX CAN2 TX
64 CAN2_RX0 CAN2 RX0
65 CAN2_RX1 CAN2 RX1
66 CAN2_SCE CAN2 SCE
67 OTG_FS USB OTG FS
68 DMA2_Stream5 DMA2 Stream 5
69 DMA2_Stream6 DMA2 Stream 6
70 DMA2_Stream7 DMA2 Stream 7
71 USART6 USART6
72 I2C3_EV I2C3 event
73 I2C3_ER I2C3 error
74 OTG_HS_EP1_OUT USB OTG HS End Point 1 Out
75 OTG_HS_EP1_IN USB OTG HS End Point 1 In
76 OTG_HS_WKUP USB OTG HS Wakeup through EXTI
77 OTG_HS USB OTG HS
78 DCMI DCMI
79 reserved reserved
80 HASH_RNG Hash and Rng
81 FPU FPU
82 UART7 UART7
83 UART8 UART8
84 SPI4 SPI4
85 SPI5 SPI5
86 SPI6 SPI6
87 SAI1 SAI1
88 LTDC LTDC
89 LTDC_ER LTDC_ER
90 DMA2D DMA2D

Clocks

UART

GPIO

Function select

Nucleo-F429ZI board

pinout

GPIO Signal description
B0 LD1 LED green
B7 LD2 LED blue
B14 LD3 LED red
D8 UART3 TX connected to ST-Link
D9 UART3 RX connected to ST-Link
A1 RMII_REF_CLK Ethernet RMII
A2 RMII_MDIO Ethernet RMII
C1 RMII_MDC Ethernet RMII
A7 RMII_MII_CRS_DV Ethernet RMII
C4 RMII_MII_RXD0 Ethernet RMII
C5 RMII_MII_RXD1 Ethernet RMII
G11 RMII_MII_TX_EN Ethernet RMII
G13 RMII_MII_TXD0 Ethernet RMII
B13 RMII_MII_TXD1 Ethernet RMII

User LED

LD1 (green)

PB0 (leuchtet wenn GPIO = 1 = High)

Kann auch auf PA5 verbunden werden per solderbridge

LD2 (blue)

PB7 (leuchtet wenn GPIO = 1 = High)

LD3 (red)

PB14 (leuchtet wenn GPIO = 1 = High)

abbreviation dictionary

abbreviation long version comment
rw read/write Software can read and write to these bits.
r read-only Software can only read these bits.
w write-only Software can only write to this bit. Reading the bit returns the reset value.
rc_w1 read/clear Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value.
rc_w0 read/clear Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value.
rc_r read/clear by read Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value.
rs read/set Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.
rt_w read-only write trigger Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value.
t toggle Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
Res. Reserved Reserved bit, must be kept at reset value.