Differences

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--- infineon:cyusb231 [ 19.05.2026 01:04] – [Variants] lars
+++ infineon:cyusb231 [ 07.06.2026 01:57] (current) – [Memory Map] lars
@@ Line 2: / Line 2: @@
 USB 2.0 @ 480MHz (High Speed)
-Package: 104 LGA
+Package: 104 LGA (8x8mm)
 Temperaure range: -45 .. 85 °C
+Operating Voltage: 1.7V to 3.6 V
 GPIF/FIFO 16bit
@@ Line 10: / Line 12: @@
 ===== Variants =====
 ^ part # ^ MCU ^ SRAM ^ Flash ^ SCB # ^ Peripherals ^
-| CYUSB2315-BF104AXI(T) | M0+(MPU) | 512 KB | 256 KB | 1 | I2C |
+| CYUSB2315-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 256 KB | 1 | I2C |
-| CYUSB2316-BF104AXI(T) | M0+(MPU) | 512 KB | 256 KB | 3 | I2C, SPI, CAN |
+| CYUSB2316-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 256 KB | 3 | I2C, SPI, CAN |
-| CYUSB2317-BF104AXI(T) | M0+(MPU) | 512 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI |
+| CYUSB2317-BF104AXI(T) | M0+(MPU)@100 MHz | 512 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI |
-| CYUSB2318-BF104AXI(T) | M4(FP,MPU)/M0+(MPU) | 1024 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI, Crypto |
+| CYUSB2318-BF104AXI(T) | M4(FP,MPU)@150 MHz/M0+(MPU)@100 MHz | 1024 KB | 512 KB | 6 | I2C, SPI, CAN, QSPI, Crypto |
+<code>
+CY = Cypress
+  USB = USB Controller
+= USB 2.0
+      xxx = part number
+         -BF104AX = LGA Package
+                 I = Industrial
+                  T = Tape and reel
+</code>
+===== Memory Map =====
+^ start address ^ end address ^ used for ^ comment ^
+| 0x00 00 00 00 | 0x01 ff ff ff | Code | Program code region. Data can also be placed here. It includes the exception vector table, which starts at address 0. |
+| 0x00 00 00 00 | 0x00 01 ff ff | ROM | size = 128 kB |
+| 0x08 00 00 00 | 0x08 01 ff ff | SRAM | size = 128 kB |
+| 0x10 00 00 00 | 0x10 07 ff ff | Internal application flash | size = up to 512 kB |
+| 0x14 00 00 00 | 0x14 00 7f ff | Auxiliary flash, can be used for EEPROM Emulation | size = 32 kB |
+| 0x16 00 00 00 | 0x16 00 7f ff | SFlash | size = 32 kB |
+| 0x1c 00 00 00 | 0x1c 0f ff ff | High bandwidth DMA buffer SRAM | size = up to 1 MB |
+| 0x20 00 00 00 | 0x3f ff ff ff | reserved | |
+| 0x40 00 00 00 | 0x5f ff ff ff | Peripheral | All peripheral registers. Code cannot be executed from this region. CM4 bit-band in this region is not supported in EZ-USBTM FX2G3. |
+| 0x60 00 00 00 | 0x9f ff ff ff | external RAM | Quad SPI: Code can be executed from this region. |
+| 0xA0 00 00 00 | 0xDf ff ff ff | external device | not used |
+| 0xe0 00 00 00 | 0xe0 0f ff ff | Private Peripheral Bus | Provides access to peripheral registers within the CPU core |
+| 0xe0 10 0a 00 | 0xff ff ff ff | device | device specific system registers |
 ===== Pins =====
@@ Line 191: / Line 220: @@
 ^ abbreviation ^ long version ^ comment ^
+| A/D | | analog-to-digital |
+| ABS | | absolute |
 | ABUS | | analog output bus |
 | AC | | alternating current |
-| ADC | | analog-to-digital converter
+| ADC | | analog-to-digital converter |
+| AES | | Advanced Encryption Standard |
 | AHB | | AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM® data transfer bus |
+| Arm® | | Advanced RISC Machine, a CPU architecture |
 | API | | application programming interface |
 | APOR | | analog power-on reset |
 | BC | | broadcast clock |
+| BD | | buffer descriptors |
+| BOD | | brownout detection |
 | BOM | | bill-of-materials |
 | BR | | bit rate |
@@ Line 203: / Line 238: @@
 | BRQ | | bus request |
 | CAN | | controller area network |
+| CAN FD | | controller area network with flexible data rate |
+| CBS | | credit-based shaping |
+| CFI | | canonical format indicator |
 | CI | | carry in |
+| CMOS | | complementary metal-oxide-semiconductor |
 | CMP | | compare |
 | CO | | carry out |
+| CPHA(SPI) | | clock phase |
+| CPOL(SPI) | | clock polarity |
 | CPU | | central processing unit |
-| CRC | | cyclic redundancy check |
+| CPUSS | | CPU subsystem |
+| CRC | | cyclic redundancy check, an error-checking protocol |
 | CSD | | CAPSENSETM sigma delta |
+| CSV | | clock supervisor |
 | CT | | continuous time |
 | CTBm | | continuous time block-mini |
 | DAC | | digital-to-analog converter |
 | DC | | direct current |
+| DDR | | double data rate (also see SDR) |
+| DES | | data encryption standard |
 | DI | | digital or data input |
 | DMA | | direct memory access |
@@ Line 220: / Line 265: @@
 | DSI | | digital signal interface |
 | DSM | | Deep Sleep mode |
+| DW | | data wire, same as P-DMA |
+| ECC | | error correcting code |
 | ECO | | external crystal oscillator |
+| EEE | | Energy Efficient Ethernet (IEEE Std 802.3az) |
 | EEPROM | | electrically erasable programmable read only memory |
 | EMIF | | external memory interface |
+| EOF | | end of frame |
+| ETM | | embedded trace macrocell |
 | FB | | feedback |
+| FCS | | frame check sequence |
 | FIFO | | first in first out |
+| FLL | | frequency locked loop |
+| FPU | | floating point unit |
 | FSR | | full scale range |
+| GHS | | Green Hills tool chain with IDE |
 | GPIO | | general purpose I/O |
 | HCI | | host-controller interface |
 | HFCLK | | high-frequency clock |
+| HSIOM | | high-speed I/O matrix |
+| HSM | | hardware security module |
 | I2C | | inter-integrated circuit |
 | IDE | | integrated development environment |
+| IF | | interface |
 | ILO | | internal low-speed oscillator |
 | IMO | | internal main oscillator |
@@ Line 237: / Line 294: @@
 | IOR | | I/O read |
 | IOW | | I/O write |
-| IRES | | initial power on reset |
+| IP | | Internet protocol |
+| IPC | | inter-processor communication |
+| IPG | | inter-packet gap |
 | IRA | | interrupt request acknowledge |
+| IrDA | | infrared interface |
+| IRES | | initial power on reset |
 | IRQ | | interrupt request |
 | ISR | | interrupt service routine |
 | IVR | | interrupt vector read |
+| JTAG | | Joint Test Action Group |
 | L2CAP | | logical link control and adaptation protocol |
+| LAN | | local area network (IEEE Std 802) |
+| LLDP | | link layer discovery protocol (IEEE Std 802.1AB) |
 | LPCOMP | | low-power comparator |
+| LPI | | low-power idle (IEEE Std 802.3az) |
 | LRb | | last received bit |
 | LRB | | last received byte |
@@ Line 249: / Line 314: @@
 | LSB | | least significant byte |
 | LUT | | lookup table |
+| LVD | | low-voltage detection |
+| MAC | | media access control (IEEE Std 802) |
+| MCU | | microcontroller unit |
+| MCWDT | | multi-counter watchdog timer |
+| M-DMA | | memory-direct memory access |
+| MDC | | management data clock |
+| MII | | media independent interface |
 | MISO | | master-in-slave-out |
 | MMIO | | memory mapped input/output |
 | MOSI | | master-out-slave-in |
+| MPU | | memory protection unit |
 | MSb | | most significant bit |
 | MSB | | most significant byte |
 | NC | Not connected | The connection may safely be used for routing space for a signal on a PCB. However, any signal connected to an NC pin must not have voltage levels higher than VIO. |
+| NSP | | non-standard preamble |
+| NVIC | | nested vectored interrupt controller |
+| OTA | | over-the-air programming |
+| OTP | | one-time programmable |
+| OVD | | overvoltage detection |
+| P-DMA | | peripheral-direct memory access same as DW |
 | PC | | program counter |
 | PCH | | program counter high |
 | PCL | | program counter low |
+| PCS | | physical coding sublayer |
 | PD | | power down |
+| PFC | | priority-based flow control (IEEE Std 802.1Qbb) |
 | PGA | | programmable gain amplifier |
+| PHY | | physical sublayer |
+| PLL | | phase-locked loop |
 | PM | | power management |
 | PMA | | PSOCTM memory arbiter |
 | POR | | power-on reset |
+| PPB | | private peripheral bus |
 | PPOR | | precision power-on reset |
+| PPPoE | | point-to-point protocol over ethernet |
+| PPU | | peripheral protection unit |
+| PRNG | | Pseudo-Random Number Generator |
 | PRS | | pseudo random sequence |
 | PSRR | | power supply rejection ratio |
 | PSSDC | | power system sleep duty cycle |
+| PTP | | precision time protocol (IEEE Std 1588) |
 | PWM | | pulse width modulator |
 | RAM | | random-access memory |
@@ Line 272: / Line 360: @@
 | RFU | Reserved for Future use | Do not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in devices with a compatible footprint. |
 | RF | | radio frequency |
+| RISC | | reduced-instruction-set computing |
 | ROM | | read only memory |
+| RTC | | real-time clock |
 | RW | | read/write |
+| RX | | reception |
 | SAR | | successive approximation register |
 | SC | | switched capacitor |
 | SCB | | serial communication block |
 | SCB | Serial Control Block | A peripheral that can be used as I2C, UART or SPI |
+| SCL | | I2C serial clock |
+| SDA | | I2C serial data |
+| SDR | | single data rate (also see DDR) |
+| SE0 | | single-ended zero |
+| SECDED | | single error correction double error detection |
+| SerDes | | serializer/deserializer |
+| SHA | | secure hash algorithm |
+| SHE | | secure hardware extension |
+| SFD | | start of frame delimiter |
+| SGMII | | serial Gigabit media independent interface |
 | SIE | | serial interface engine |
 | SIO | | special I/O |
-| SE0 | | single-ended zero |
+| SMIF | | serial memory interface |
+| SMPU | | shared memory protection unit |
+| SNAP | | subnetwork access protocol |
 | SNR | | signal-to-noise ratio |
 | SOF | | start of frame |
@@ Line 286: / Line 389: @@
 | SP | | stack pointer |
 | SPD | | sequential phase detector |
+| SPI | | serial peripheral interface, a communications protocol |
 | SPI | | serial peripheral interconnect |
 | SPIM | | serial peripheral interconnect master |
@@ Line 296: / Line 400: @@
 | SYSCLK | | system clock |
 | SWD | | single wire debug |
+| Tbit | | bit period |
 | TC | | terminal count |
+| TCP | | transfer control protocol |
+| TCPWM | | timer/counter pulse-width modulator |
 | TD | | transaction descriptors |
-| UART | | universal asynchronous receiver/transmitter |
+| TTL | | transistor-transistor logic |
+| TRNG | | True Random Number Generator |
+| TS | | timestamp |
+| TSU | | timestamp unit|
+| TX | | transmission |
+| UART | | Universal Asynchronous Transmitter Receiver, a communications protocol |
 | UDB | | universal digital block |
+| UDP | | user datagram protocol |
 | USB | | Universal Serial Bus |
 | USBIO | | USB I/O |
+| VLAN | | Virtual LAN (IEEE Std 802.1Q) |
 | WCO | | watch crystal oscillator |
-| WDT | | watchdog timer |
+| WDT | | watchdog timer / watchdog timer reset |
 | WDR | | watchdog reset |
+| XIP | | execute-in-place |
 | XRES | | external reset |
 | XRES_N | | external reset, active LOW |
+| XRES_L | | external reset I/O pin (active LOW) |
+| XTAL | | crystal |