Differences

This shows you the differences between two versions of the page.

--- ref:cortex_m0p [ 02.03.2026 22:59] – created lars
+++ ref:cortex_m0p [ 06.04.2026 13:28] (current) – [Memory Map] lars
@@ Line 2: / Line 2: @@
 ===== Memory Map =====
-^ start address ^ end address ^ used for ^ comment ^
+|< 100% 20% 20% 20% 40% >|
+^  start address  ^  end address  ^  used for  ^  comment  ^
 | 0x00 00 00 00 | 0x1F FF FF FF | **Code** | |
 | 0x20 00 00 00 | 0x3F FF FF FF | **SRAM** | |
@@ Line 53: / Line 54: @@
 | 0xE0 00 ED A0 |  | MPU_RASR | MPU Region Attribute and Size Register |
 | 0xE0 00 ED F0 | 0xE0 00 EE FF | **Debug Control Block** | |
-| 0xE0 00 ED F0 |  | [[arm:cortex_m0p#DHCSR - Debug Halting Control and Status Register|DHCSR]] | Debug Halting Control and Status |
+| 0xE0 00 ED F0 |  | [[cortex_m0p#DHCSR - Debug Halting Control and Status Register|DHCSR]] | Debug Halting Control and Status |
 | 0xE0 00 ED F4 |  | DCRSR | Debug Core Register Selector Register |
 | 0xE0 00 ED F8 |  | DCRDR | Debug Core Register Data Register |
@@ Line 59: / Line 60: @@
 | 0xE0 00 EF 00 | 0xE0 00 EF 03 | **Nested Vectored Interrupt Controller** | |
 | 0xE0 00 EF 90 | 0xE0 00 EF CF | implementation defined | |
-| 0xE0 0F F0 00 | 0xE0 0F FF FF | **[[arm:cortex_m0p#ROM Table|ARMv6-M ROM table]]** | |
+| 0xE0 0F F0 00 | 0xE0 0F FF FF | **[[cortex_m0p#ROM Table|ARMv6-M ROM table]]** | |
 | 0xE0 10 00 00 | 0xFF FF FF FF | **Vendor_SYS** | |