ARM Cortex-M 0+

Memory Map

start address	end address	used for	comment
0x00 00 00 00	0x1F FF FF FF	Code
0x20 00 00 00	0x3F FF FF FF	SRAM
0x40 00 00 00	0x5F FF FF FF	Peripheral
0x60 00 00 00	0x7F FF FF FF	RAM
0x80 00 00 00	0x9F FF FF FF	RAM
0xA0 00 00 00	0xBF FF FF FF	Device
0xC0 00 00 00	0xDF FF FF FF	Device
0xE0 00 00 00	0xFF FF FF FF	System
0xE0 00 00 00	0xE0 0F FF FF	PPB	Private Peripheral Bus
0xE0 00 10 00	0xE0 00 1F FF	Data Watchpoint and Trace
0xE0 00 10 00	DWT_CTRL
0xE0 00 10 1C	DWT_PCSR	Program Counter Sample Register
0xE0 00 10 20	DWT_COMPx	Comparator registers
0xE0 00 10 24	DWT_MASKx	Comparator Mask Registers
0xE0 00 10 28	DWT_FUNCTIONx	Comparator Function Registers
0xE0 00 20 00	0xE0 00 2F FF	Breakpoint unit
0xE0 00 20 00	BP_CTRL
0xE0 00 20 08	BP_COMPx	Breakpoint Comparator registers
0xE0 00 E0 00	0xE0 00 EF FF	System Control Space
0xE0 00 E0 08	0xE0 00 E0 0F	System Control Block
0xE0 00 E0 08	ACTLR	Auxiliary Control Register
0xE0 00 E0 10	0xE0 00 E0 FF	SysTick	optional
0xE0 00 E0 10	SYST_CSR	SysTick Control and Status Register
0xE0 00 E0 14	SYST_RVR	SysTick Reload Value Register
0xE0 00 E0 18	SYST_CVR	SysTick Current Value Register
0xE0 00 E0 1C	SYST_CALIB	SysTick Calibration Value Register
0xE0 00 E1 00	0xE0 00 EC FF	Nested Vectored Interrupt Controller
0xE0 00 E1 00	NVIC_ISER	Interrupt Set-Enable Register
0xE0 00 E1 80	NVIC_ICER	Interrupt Clear-Enable Register
0xE0 00 E2 00	NVIC_ISPR	Interrupt Set-Pending Register
0xE0 00 E2 80	NVIC_ICPR	Interrupt Clear-Pending Register
0xE0 00 E4 00	0xE0 00 E4 EF	NVIC_IPRO0-7	Interrupt Priority Registers
0xE0 00 ED 00	0xE0 00 ED 8F	System Conrol Block
0xE0 00 ED 00	CPUID
0xE0 00 ED 04	ICSR	Interrupt Control and State Register
0xE0 00 ED 08	VTOR	Vector Table Offset Register (optional)
0xE0 00 ED 0C	AIRCR	Application Interrupt and Reset Control Register
0xE0 00 ED 10	SCR	System Control Register
0xE0 00 ED 14	CCR	Configuration and Control Register
0xE0 00 ED 1C	SHPR2	System Handler Priority Register 2
0xE0 00 ED 20	SHPR3	System Handler Priority Register 3
0xE0 00 ED 24	SHCSR	System Handler Control and State Register
0xE0 00 ED 30	DFSR	Debug Fault Status Register
0xE0 00 ED 90	0xE0 00 ED EF	Memory Protection Unit	optional
0xE0 00 ED 90	MPU_TYPE
0xE0 00 ED 94	MPU_CTRL	MPU Control Register
0xE0 00 ED 98	MPU_RNR	MPU Region Number Register
0xE0 00 ED 9C	MPU_RBAR	MPU Region Base Address Register
0xE0 00 ED A0	MPU_RASR	MPU Region Attribute and Size Register
0xE0 00 ED F0	0xE0 00 EE FF	Debug Control Block
0xE0 00 ED F0	DHCSR	Debug Halting Control and Status
0xE0 00 ED F4	DCRSR	Debug Core Register Selector Register
0xE0 00 ED F8	DCRDR	Debug Core Register Data Register
0xE0 00 ED FC	DEMCR	Debug Exception and Monitor Control Register
0xE0 00 EF 00	0xE0 00 EF 03	Nested Vectored Interrupt Controller
0xE0 00 EF 90	0xE0 00 EF CF	implementation defined
0xE0 0F F0 00	0xE0 0F FF FF	ARMv6-M ROM table
0xE0 10 00 00	0xFF FF FF FF	Vendor_SYS

ROM Table

offset	name	value	description
0x000	SCS	0xFF F0 F0 03	Points to the System Control Space(SCS) at 0xE0 00 E0 00
0x004	ROMDWT	0xFF F0 20 02 or 0xFF F0 20 03	points to the Data Watchpoint and Trace(DWT) at 0xE0 00 10 00
0x008	ROMBPU	0xFF F0 30 02 or 0xFF F0 30 03	points to the Breakpoint unit(BPU) at 0xE0 00 20 00
0x00C	End	0x00 00 00 00	End of table marker.
0x010 - 0xffc	reserved	0x00 00 00 00	reserved (read as 0)

each entry (32bit) adheres to this format:

bits	name	description
31 - 12	address offset	signed base address offset of the component relative to the ROM base address
11 - 2	reserved
1	format	0 = 8 bit (not used) ; 1 = 32 bit
0	entry present	1 = valid entry; 0 = entry not valid or end of table

DHCSR - Debug Halting Control and Status Register

write:

bits	name	description
31 - 16	DBGKEY	must be 0xa05f
15 - 4	reserved
3	C_MASKINTS	0 = do not mask; 1 = mask PendSV, SysTick and external configurable interrupts
2	C_STEP	0 = single stepping disabled; 1 = single stepping enabled
1	C_HALT	0 = request a halted processor to run; 1 = request a running processor to halt
0	C_DEBUGEN	0 = halting debug disabled; 1 = halting debug enabled

read:

bits	name	description
31 - 26	reserved
25	S_RESET_ST	0 = no processor reset since last DHCSR read; 1 = at least one processor reset since last read of DHCSR
24	S_RETIRE_ST	0 = no instruction executed since last read of DHCSR; 1 = at least one instruction executed since last read of DHCSR
23 - 20	reserved
19	S_LOOKUP	0 = no lookup; 1 = processor in unrecoverable exception
18	S_SLEEP	0 = not sleeping; 1 = sleeping
17	S_HALT	0 = not in debug state; 1 = in debug state
16	S_REGRDY	0 = write to DCRDR but transfer is not complete; 1 = the transfer to/from DCRDR is complete
15 - 4	reserved
3	C_MASKINTS	0 = do not mask; 1 = mask PendSV, SysTick and external configurable interrupts
2	C_STEP	0 = single stepping disabled; 1 = single stepping enabled
1	C_HALT	0 = request a halted processor to run; 1 = request a running processor to halt
0	C_DEBUGEN	0 = halting debug disabled; 1 = halting debug enabled