Differences

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--- stm:stm32f429 [ 07.03.2026 10:12] – [User LED] lars
+++ stm:stm32f429 [ 19.04.2026 09:55] (current) – [abbreviation dictionary] lars
@@ Line 2: / Line 2: @@
 ARM Cortex-M4 (180MHz) FPU
 ===== Memory Map =====
-^ start address ^ end address ^  used for ^  comment ^
+|< 100% 15% 15% 20% 50% >|
+^ start address ^ end address ^  used for  ^  comment  ^
 |  0x0 |  0x1fffff | | Aliased to flash, system memory or SRAM depending on the BOOT pins |
 |  0x20 0000 |  0x7ff ffff | reserved | |
@@ Line 132: / Line 133: @@
 ==== IRQ ====
-^ IRQ Number ^ Signal ^
+^ IRQ Number ^ Signal ^ Description ^
+| 0 | WWDG | Window WatchDog |
+| 1 | PVD | PVD through EXTI Line detection |
+| 2 | TAMP_STAMP | Tamper and TimeStamps through the EXTI line |
+| 3 | RTC_WKUP | RTC Wakeup through the EXTI line |
+| 4 | FLASH | FLASH Handler |
+| 5 | RCC_IRQHandler | RCC |
+| 6 | EXTI0 | EXTI Line0 |
+| 7 | EXTI1 | EXTI Line1 |
+| 8 | EXTI2 | EXTI Line2 |
+| 9 | EXTI3 | EXTI Line3 |
+| 10 | EXTI4 | EXTI Line4 |
+| 11 | DMA1_Stream0 | DMA1 Stream 0 |
+| 12 | DMA1_Stream1 | DMA1 Stream 1 |
+| 13 | DMA1_Stream2 | DMA1 Stream 2 |
+| 14 | DMA1_Stream3 | DMA1 Stream 3 |
+| 15 | DMA1_Stream4 | DMA1 Stream 4 |
+| 16 | DMA1_Stream5 | DMA1 Stream 5 |
+| 17 | DMA1_Stream6 | DMA1 Stream 6 |
+| 18 | ADC | ADC1, ADC2 and ADC3s |
+| 19 | CAN1_TX | CAN1 TX |
+| 20 | CAN1_RX0 | CAN1 RX0 |
+| 21 | CAN1_RX1 | CAN1 RX1 |
+| 22 | CAN1_SCE | CAN1 SCE |
+| 23 | EXTI9_5 | External Line[9:5]s |
+| 24 | TIM1_BRK_TIM9 | TIM1 Break and TIM9 |
+| 25 | TIM1_UP_TIM10 | TIM1 Update and TIM10 |
+| 26 | TIM1_TRG_COM_TIM11 | TIM1 Trigger and Commutation and TIM11 |
+| 27 | TIM1_CC | TIM1 Capture Compare |
+| 28 | TIM2 | TIM2 |
+| 29 | TIM3 | TIM3 |
+| 30 | TIM4 | TIM4 |
+| 31 | I2C1_EV | I2C1 Event |
+| 32 | I2C1_ER | I2C1 Error |
+| 33 | I2C2_EV | I2C2 Event |
+| 34 | I2C2_ER | I2C2 Error |
+| 35 | SPI1 | SPI1 |
+| 36 | SPI2 | SPI2 |
+| 37 | USART1 | USART1 |
+| 38 | USART2 | USART2 |
+| 39 | USART3 | USART3 |
+| 40 | EXTI15_10 | External Line[15:10]s |
+| 41 | RTC_Alarm | RTC Alarm (A and B) through EXTI Line |
+| 42 | OTG_FS_WKUP | USB OTG FS Wakeup through EXTI line |
+| 43 | TIM8_BRK_TIM12 | TIM8 Break and TIM12 |
+| 44 | TIM8_UP_TIM13 | TIM8 Update and TIM13 |
+| 45 | TIM8_TRG_COM_TIM14 | TIM8 Trigger and Commutation and TIM14 |
+| 46 | TIM8_CC | TIM8 Capture Compare |
+| 47 | DMA1_Stream7 | DMA1 Stream7 |
+| 48 | FMC | FMC |
+| 49 | SDIO |SDIO |
+| 50 | TIM5 | TIM5 |
+| 51 | SPI3 | SPI3 |
+| 52 | UART4 | UART4 |
+| 53 | UART5 | UART5 |
+| 54 | TIM6_DAC | TIM6 and DAC1&2 underrun errors |
+| 55 | TIM7 | TIM7 |
+| 56 | DMA2_Stream0 | DMA2 Stream 0 |
+| 57 | DMA2_Stream1 | DMA2 Stream 1 |
+| 58 | DMA2_Stream2 | DMA2 Stream 2 |
+| 59 | DMA2_Stream3 | DMA2 Stream 3 |
+| 60 | DMA2_Stream4 | DMA2 Stream 4 |
+| 61 | ETH | Ethernet |
+| 62 | ETH_WKUP | Ethernet Wakeup through EXTI line |
+| 63 | CAN2_TX | CAN2 TX |
+| 64 | CAN2_RX0 | CAN2 RX0 |
+| 65 | CAN2_RX1 | CAN2 RX1 |
+| 66 | CAN2_SCE | CAN2 SCE |
+| 67 | OTG_FS | USB OTG FS |
+| 68 | DMA2_Stream5 | DMA2 Stream 5 |
+| 69 | DMA2_Stream6 | DMA2 Stream 6 |
+| 70 | DMA2_Stream7 | DMA2 Stream 7 |
+| 71 | USART6 | USART6 |
+| 72 | I2C3_EV | I2C3 event |
+| 73 | I2C3_ER | I2C3 error |
+| 74 | OTG_HS_EP1_OUT | USB OTG HS End Point 1 Out |
+| 75 | OTG_HS_EP1_IN | USB OTG HS End Point 1 In |
+| 76 | OTG_HS_WKUP | USB OTG HS Wakeup through EXTI |
+| 77 | OTG_HS | USB OTG HS |
+| 78 | DCMI | DCMI |
+| 79 | reserved | reserved |
+| 80 | HASH_RNG | Hash and Rng |
+| 81 | FPU | FPU |
+| 82 | UART7 | UART7 |
+| 83 | UART8 | UART8 |
+| 84 | SPI4 | SPI4 |
+| 85 | SPI5 | SPI5 |
+| 86 | SPI6 | SPI6 |
+| 87 | SAI1 | SAI1 |
+| 88 | LTDC | LTDC |
+| 89 | LTDC_ER | LTDC_ER |
+| 90 | DMA2D | DMA2D |
 ==== Clocks ====
@@ Line 146: / Line 237: @@
 ====== Nucleo-F429ZI board ======
+===== pinout =====
+^ GPIO ^ Signal ^ description ^
+| B0 | LD1 | LED green |
+| B7 | LD2 | LED blue  |
+| B14 | LD3 | LED red |
+| D8 | UART3 TX | connected to ST-Link |
+| D9 | UART3 RX |connected to ST-Link |
+| A1 | RMII_REF_CLK | Ethernet RMII |
+| A2 | RMII_MDIO | Ethernet RMII |
+| C1 | RMII_MDC | Ethernet RMII |
+| A7 | RMII_MII_CRS_DV | Ethernet RMII |
+| C4 | RMII_MII_RXD0 | Ethernet RMII |
+| C5 | RMII_MII_RXD1 | Ethernet RMII |
+| G11 | RMII_MII_TX_EN | Ethernet RMII |
+| G13 | RMII_MII_TXD0 | Ethernet RMII |
+| B13 | RMII_MII_TXD1 |Ethernet RMII |
 ===== User LED =====
@@ Line 162: / Line 271: @@
 ^ abbreviation ^ long version ^ comment ^
+| rw | read/write | Software can read and write to these bits. |
+| r | read-only | Software can only read these bits. |
+| w | write-only | Software can only write to this bit. Reading the bit returns the reset value. |
+| rc_w1 | read/clear | Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. |
+| rc_w0 | read/clear | Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. |
+| rc_r | read/clear by read | Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. |
+| rs | read/set | Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. |
+| rt_w | read-only write trigger | Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value. |
+| t | toggle | Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. |
+| Res. | Reserved | Reserved bit, must be kept at reset value. |